1. Field of the Invention
This invention relates to a solid-state imaging device and more particularly to a solid-state imaging device such as a CMOS sensor formed by the CMOS technology.
2. Description of the Related Art
A solid-state imaging device has unit pixels arranged in a two-dimensional matrix form in an imaging area. FIG. 1 shows the cross sectional structure of one unit pixel of a conventional solid-state imaging device which is generally called a CMOS sensor.
A p-type well region (p-well) 32 is formed on a p-type silicon substrate 31. On the surface portion of the well region 32, a photo-electric conversion region 35 formed of a p+-type diffused layer 33 and n-type diffused layer 34 is formed. The n-type diffused layer 34 constitutes a signal accumulation portion for accumulating signal charges obtained by photo-electrical conversion of input light and the p+-type diffused layer 33 is formed to serve the purpose of preventing occurrence of a dark current.
A gate electrode 36 for controlling readout of the signal charge accumulated in the n-type diffused layer 34 constituting the signal accumulation portion is formed adjacent to the photo-electric conversion region 35. Further, an n-type diffused layer 37 used as a signal detection portion for detecting the signal charge transferred via a channel region lying below the gate electrode 36 is formed adjacent to the gate electrode 36. In addition, a gate electrode 38 for controlling transfer of the signal charge detected by the n-type diffused layer 37 is formed adjacent to the n-type diffused layer 37.
An amplifying MOS field effect transistor (the MOS field effect transistor is hereinafter referred to as a MOS transistor) 42 having a drain region 39 and source region 40 which are formed of n-type diffused layers and a gate electrode 41 is formed adjacent to the gate electrode 38. The gate electrode 41 of the amplifying MOS transistor 42 is connected to the n-type diffused layer 37 via an interconnection 43. A MOS transistor 45, which is a row select switch, is connected to the MOS transistor 42 in series. The source region 46 of the MOS transistor 45 is connected to a signal read-out line 44. In order to simplify the drawing, gate insulating films and interlayer dielectrics are omitted in the drawing.
Next, the operation of the unit pixel with the above cross sectional structure is explained.
During the signal accumulation period, a signal charge is generated according to input light incident on the photo-electric conversion region 35 and accumulated in the signal accumulation portion (n-type diffused layer 34). In the signal readout period after the end of the signal accumulation period, the readout gate electrode 36 is set into the ON state and the signal charge is discharged from the signal accumulation portion to the signal detection portion (n-type diffused layer 37) via the channel region lying below the gate electrode 36. In the signal detection portion, the signal charge is converted into signal voltage and the thus converted signal voltage is supplied to the gate electrode 41 of the amplifying MOS transistor 42 via the interconnection 43. The signal voltage is amplified by the MOS transistor 42 and read out from the readout line 44 connected to the source region 46 of the MOS transistor 45.
FIG. 2A is a cross sectional view showing the structure of an extracted portion including the signal accumulation portion (n-type diffused layer 34), signal detection portion (n-type diffused layer 37) and the surrounding portion of the unit pixel shown in FIG. 1 and FIG. 2B shows the state in which the signal charge is discharged from the signal accumulation portion (n-type diffused layer 34) to the signal detection portion (n-type diffused layer 37) and then the signal charge is read out in the signal readout period of the unit pixel shown in FIG. 2A by use of a potential diagram.
When the readout gate electrode 36 is set in the OFF state, a potential of the channel region below the gate electrode 36 becomes low and the signal charge accumulated in the signal accumulation portion (n-type diffused layer 34) is kept accumulated. If a readout potential for setting the gate electrode 36 into the ON state is supplied to the readout gate electrode 36, a potential of the channel region below the gate electrode 36 becomes high, the signal charge accumulated in the signal accumulation portion (n-type diffused layer 34) is discharged into the signal detection portion (n-type diffused layer 37) via the channel region and thus the signal charge is read out.
However, the conventional pixel has the following problems.
That is, when the readout operation is effected by discharging the signal charge into the signal detection portion, a potential of the channel region lying below the gate electrode 36 becomes high and a potential of a neighboring portion of the signal accumulation portion adjacent to the gate electrode 36 is accordingly modulated so that the signal charge can be read out from the signal accumulation portion.
However, since the p+-type diffused layer 33 used for preventing occurrence of a dark current is formed, the potential of the neighboring portion of the signal accumulation portion which lies near the readout gate electrode 36 becomes difficult to be modulated according to the gate potential of the gate electrode 36. Therefore, as shown in FIG. 2B, a potential barrier which acts as an obstacle when the signal charge is discharged is formed under the edge portion of the readout gate electrode 36. As a result, part of the signal charge is left behind as the residual charge in the signal accumulation portion and the signal readout operation cannot be perfectly effected.
If the signal readout operation from the signal accumulation portion cannot be perfectly effected, a problem that the dynamic range of the imaging device is lowered and a problem that thermal noise of a dark potion increases and an image-lag occurs on the reproduced screen, and therefore, the quality of the reproduced image is extremely degraded. In addition, the above problems appear more significantly as the pixel size is further reduced.
According to the request for enhancing the quality of a reproduced image and reducing the element size, the size of the unit pixel tends to be reduced year by year. As the size of the unit pixel is reduced, the size of the MOS transistor is reduced accordingly, but a reduction in the element size is generally accompanied by a lowering in the application voltage and a rise in the impurity concentration of the well region according to the scaling-down rule.
However, if the scaling-down process is thus effected, a region which can be subjected to the potential modulation by the gate electrode is limited only to a portion near the gate electrode and is thus made narrower. Therefore, the potential modulation in a portion lying near the gate electrode 36 and neighboring to the signal accumulation portion (n-type diffused layer 34) which is formed in position deeper than the p+-type diffused layer 33 formed on the surface becomes difficult to occur. As a result, the above-described potential barrier tends to occur more likely in the miniaturized pixel and the above problem inherent to the CMOS sensor becomes more significant.
Further, the following problem occurs in the conventional case. That is, as described above, it is preferable to form the p+-type diffused layer 33 on the surface in the shallowest possible portion so that the potential modulation in a portion near the gate electrode 36 of the signal accumulation portion (n-type diffused layer 34) can be easily attained. However, if the p+-type diffused layer 33 is form in the shallow position, the dark current occurring in the substrate surface tends to increase, and as a result, noise occurs on the reproduction screen.
As described above, in the conventional solid-state imaging device, the readout potential applied to the signal charge readout gate electrode is lowered as the unit pixel is miniaturized and if the impurity concentration of the well region which is formed below the gate electrode and in which the channel region is formed is increased, there occurs a problem that the operation for reading the signal charge from the signal accumulation portion cannot be effected to a sufficient degree and thermal noise at the dark time, dark current noise, image-lag and the like will occur.
Therefore, it is required to realize a solid-state imaging device which can permit the operation for reading the signal charge from the signal accumulation portion to be easily effected and prevent thermal noise, dark current noise, image-lag and the like from occurring even when the readout potential applied to the readout gate electrode is lowered as the unit pixel is miniaturized and if the impurity concentration of the well region which is formed below the gate electrode and in which the channel region is formed is increased.
A solid-state imaging device according to a first aspect of this invention comprises a semiconductor substrate including a surface region of a second conductivity type; and a plurality of unit pixels arranged in a matrix form on the surface region of the second conductivity type, the plurality of unit pixels forming an imaging area and each of the plurality of unit pixels including a first semiconductor region of a first conductivity type which is formed in a position separated by a preset distance from a surface of the surface region in a depth direction of the surface region and accumulates signal charges obtained by photo-electrical conversion of input light, and a gate electrode which is formed adjacent to the first semiconductor region above the surface region and controls readout of the signal charges accumulated in the first semiconductor region, end portions of the gate electrode and the first semiconductor region which substantially face each other being formed in positions separated by a preset distance in a horizontal direction.
A solid-state imaging device according to a second aspect of this invention comprises a semiconductor substrate including a surface region of a second conductivity type; and a plurality of unit pixels arranged in a matrix form on the surface region of the second conductivity type, the plurality of unit pixels forming an imaging area and each of the plurality of unit pixels including a first semiconductor region of a first conductivity type which is formed in a position separated by a preset distance from a surface of the surface region in the depth direction of the surface region and accumulates signal charges obtained by photo-electrical conversion of input light, a gate electrode which is formed adjacent to the first semiconductor region above the surface region and controls readout of the signal charges accumulated in the first semiconductor region, end portions of the gate electrode and the first semiconductor region which substantially face each other being formed in positions separated by a preset distance in a horizontal direction, and a second semiconductor region of the first conductivity type which is formed in a channel region lying on an upper surface of the surface region and below the gate electrode and controls a threshold voltage of the gate electrode, the second semiconductor region being formed in a position separated from the first semiconductor region with the surface region disposed between the first and the second semiconductor region.
A solid-state imaging device according to a third aspect of this invention comprises a semiconductor substrate including a surface region of a second conductivity type; and a plurality of unit pixels arranged in a matrix form on the surface region, the plurality of unit pixels forming an imaging area and each of the plurality of unit pixels including a first semiconductor region of a first conductivity type which is formed in a position separated by a preset distance from a surface of the surface region in a depth direction of the surface region and accumulates signal charges obtained by photo-electrical conversion of input light, a gate electrode which is formed adjacent to the first semiconductor region above the surface region and controls readout of the signal charges accumulated in the first semiconductor region, and a fourth semiconductor region of the first conductivity type which is formed adjacent to the gate electrode and detects the signal charges read out by the gate electrode and transferred via a channel region below the gate electrode; wherein a potential of the channel region below the gate electrode is set to the same potential as that of the first semiconductor region when a readout potential is supplied to the gate electrode to set the gate electrode into an ON state and the potential of the channel region is set lower than that of the fourth semiconductor region when the gate electrode is set in an OFF state.